MR3I=Disabled, MR1S=Disabled, MR3S=Disabled, MR1I=Disabled, MR2I=Disabled, MR3R=Disabled, MR2S=Disabled, MR0S=Disabled, MR2R=Disabled, MR0R=Disabled, MR1R=Disabled, MR0I=Disabled
Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
| MR0I | Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR0R | Reset on MR0: the TC will be reset if MR0 matches it. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR0S | Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR1I | Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR1R | Reset on MR1: the TC will be reset if MR1 matches it. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR1S | Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR2I | Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR2R | Reset on MR2: the TC will be reset if MR2 matches it. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR2S | Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR3I | Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR3R | Reset on MR3: the TC will be reset if MR3 matches it. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| MR3S | Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 (Disabled): Disabled 1 (Enabled): Enabled |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |